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HD74LS195A
4-bit Parallel-Access Shift Register
REJ03D0457-0300 Rev.3.00 Jul.15.2005 This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of operation: * Parallel (broadside) load * Shift (in the direction QA toward QD) Parallel loading is accomplished by applying the four bits of data and taking the shift / load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift / load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D-, or Ttype flip-flop as shown in the function table.
Features
* Ordering Information
Part Name HD74LS195AFPEL Package Type SOP-16 pin (JEITA) Package Code (Previous Code) PRSP0016DH-B (FP-16DAV) Package Abbreviation FP Taping Abbreviation (Quantity) EL (2,000 pcs/reel)
Pin Arrangement
Clear Serial Inputs J K A Parallel Inputs B C D GND
1
Clear
16
J K A B C QA QB QC QD QD
VCC QA QB QC QD QD Clock Shift/Load Outputs
2 3 4 5 6 7 8
15 14 13 12 11 10 9
D CK Shift/Load
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 7
HD74LS195A
Function Table
Clear L H H H H H H Notes: 1. 2. 3. 4. Shift / Load X L H H H H H Clock X L Inputs Serial J K X X X X X X L H L L H H H L Outputs A X a X X X X X Parallel B C X X b c X X X X X X X X X X D X d X X X X X QA L a QA0 QA0 L H QAn QB L b QB0 QA0 QAn QAn QAn QC L c QC0 QBn QBn QBn QBn QD L d QD0 QCn QCn QCn QCn QD H d QD0 QCn QCn QCn QCn
H; high level, L; low level, X; irrelevant ; transition from low to high level a to d; the level of steady-state input at inputs A, B, C, or D, respectively QA0 to QD0; the level of QA, QB, QC, or QD, respectively before the indicated steady-state input conditions were established. 5. QAn to QCn; the level of QA, QB, QC, respectively before the most-recent transition of the clock.
Block Diagram
Serial Inputs J K Shift/Load Control Parallel Inputs A B C D
Clock Clear Clear R QA CK S QA Clear R CK S QB Clear R CK S QC Clear R QD CK S QD
QA
QB
QC
QD QD
parallel Outputs
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.3.00, Jul.15.2005, page 2 of 7
HD74LS195A
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Clear pulse width Shift / load Setup time Serial and parallel data Clear inactive-state Release time Hold time trelease th tsu Symbol VCC IOH IOL Topr clock tw (CK) tsu (CLR) Min 4.75 -- -- -20 0 16 12 25 15 25 -- 0 Typ 5.00 -- -- 25 -- -- -- -- -- -- -- -- Max 5.25 -400 8 75 30 -- -- -- -- -- 5 -- Unit V A mA C MHz ns ns ns ns ns ns ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II min. 2.0 -- 2.7 -- -- -- -- -- typ.* -- -- -- -- -- -- -- -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 Unit V V V V A mA mA Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V
Input current
Short-circuit output IOS -20 -- -100 mA VCC = 5.25 V current Supply current** ICC -- 14 21 mA VCC = 5.25 V Input clamp voltage VIK -- -- -1.5 V VCC = 4.75 V, IIN = -18 mA Notes: * VCC = 5 V, Ta = 25C ** With all outputs open, shift / load grounded, and 4.5 V applied to the J, K, and data inputs, ICC is measured by applying a momentary ground, followed by 4.5 V, to clear and then applying a momentary ground, followed by 4.5 V, to clock.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Propagation delay time Symbol max tPHL tPLH tPHL Inputs Clock Clear Clock Outputs QA to QD QA to QD QA to QD QD min. 30 -- -- -- typ. 39 19 14 17 max. -- 30 22 26 Unit MHz ns ns ns Condition CL = 15 pF, RL = 2 k
Rev.3.00, Jul.15.2005, page 3 of 7
HD74LS195A
Count Sequence
Clock Clear Serial Inputs J K
Shift Load A Parallel Data Inputs B C D QA QB Outputs QC QD Serial Shift Clear Load Serial Shift H L H L
Rev.3.00, Jul.15.2005, page 4 of 7
HD74LS195A
Testing Method
Test Circuit
VCC
4.5V
Output RL QA Load circuit 1
Input P.G. Zout = 50
CK Shift/Load
CL Output QB Output QC Output QD Output QD Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1.
See Testing Table
J K A B C D CLR
Input P.G. Zout = 50
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Testing Table
Inputs Item max tPLH tPHL Clear QA to QD Clock QA to QD, QD From input to output CLR 4.5V IN 4.5V 4.5V Shift / Load 4.5V GND 4.5V GND J 4.5V 4.5V 4.5V 4.5V K GND 4.5V GND 4.5V CK IN IN IN IN Outputs QA OUT OUT OUT OUT QB OUT OUT OUT OUT QC OUT OUT OUT OUT QD OUT OUT OUT OUT QD OUT -- OUT OUT A 4.5V 4.5V 4.5V IN B 4.5V 4.5V 4.5V IN C 4.5V 4.5V 4.5V IN D 4.5V 4.5V 4.5V IN
Item max tPLH tPHL
From input to output
Clear QA to QD Clock QA to QD, QD
Rev.3.00, Jul.15.2005, page 5 of 7
HD74LS195A Waveform
tw (CLR) tTHL tTLH 90% 1.3V 10% tsu tTHL 1.3V 10% tsu 1.3V tsu trelease tn 1.3V th
Clear
90% 1.3V 10% tTLH
3V 0V
tn+1 tn 1.3V tn+1
3V 0V
Clock
10%
90% 90% 1.3V tw (CK)
tsu 1.3V tsu
th
3V
1.3V
Data
1.3V
0V
trelease 1.3V tPLH 1.3V
3V 0V
Shift/Load
1.3V tPHL
1.3V
tPHL
VOH Outputs Q
1.3V 1.3V 1.3V
VOL
Notes:
1. Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50% 2. A clear pulse is applied prior to each test. 3. Propagation delay times (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified at tn + 4 with a functional test. 4. J and K inputs are tested the same as data A, B, C, and D inputs except that shift / load input remains high. 5. tn; bit time beroer clocking transition. 6. tn + 1; bit time after one clocking transition. 7. tn + 4; bit time after four clocking transition.
Rev.3.00, Jul.15.2005, page 6 of 7
HD74LS195A
Package Dimensions
JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B Previous Code FP-16DAV MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jul.15.2005, page 7 of 7
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